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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 123 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? high endurance non-volatile memory segments ? 4k/8k bytes of in-system self-progra mmable flash program memory(attiny48/88) ? 64/64 bytes eepr om (attiny48/88) ? 256/512 bytes internal sram (attiny48/88) ? write/erase cycles: 10,000 flash/100,000 eeprom ? data retention: 20 years at 85 c / 100 years at 25 c ? optional boot code section with indepentent lock bits ? in-system programming by on-chip boot program ? true read-while-w rite operation ? programming lock for software security ? peripheral features ? one 8-bit timer/counter with se parate prescaler and compare mode ? one 16-bit timer/counter with presc aler, and compare and capture modes ? 8-channel 10-bit adc in 32-lead tqfp and 32-pad qfn/mlf package ? 6-channel 10-bit adc in 28-pin pdip and 28-pad qfn/mlf package ? master/slave spi serial interface ? byte-oriented 2-wire se rial interface (philips i 2 c compatible) ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? three sleep modes: idle, adc noise reduction and power-down ? i/o and packages ? 28 programmable i/o lines in 32-lead tqfp and 32-pad qfn/mlf package ? 24 programmable i/o lines in 28-pin pdip and 28-pad qfn/mlf package ? 28-pin pdip, 32-lead tqfp, 28-p ad qfn/mlf and 32-pad qfn/mlf ? operating voltage: ?1.8 ? 5.5v ? temperature range: ?-40 c to +85 c ? speed grade: ?0 ? 2 mhz @ 1.8 ? 5.5v ?0 ? 6 mhz @ 2.7 ? 5.5v ?0 ? 12 mhz @ 4.5 ? 5.5v ? low power consumption ? active mode: 1 mhz, 1.8v: 240a ? power-down mode: 0.1a at 1.8v 8-bit microcontroller with 4/8k bytes in-system programmable flash attiny48/88 preliminary summary rev. 8008bs?avr?06/08
2 8008bs?avr?06/08 attiny48/88 1. pin configurations figure 1-1. pinout of attiny48/88 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (pcint19/int1) pd3 (pcint20/t0) pd4 (pcint26) pa2 vcc gnd (pcint27) pa3 (pcint6/clki) pb6 (pcint7) pb7 pc1 (adc1/pcint9) pc0 (adc0/pcint8) pa1 (adc7/pcint25) gnd pc7 (pcint15) pa0 (adc6/pcint24) avcc pb5 (sck/pcint5) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (pcint21/t1) pd5 (pcint22/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (pcint17) pd0 (pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (pcint14/reset) pc6 (pcint16) pd0 (pcint17) pd1 (pcint18/int0) pd2 (pcint19/int1) pd3 (pcint20/t0) pd4 vcc gnd (pcint6/clki) pb6 (pcint7) pb7 (pcint21/t1) pd5 (pcint22/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) pc1 (adc1/pcint9) pc0 (adc0/pcint8) gnd pc7 (pcint15) avcc pb5 (sck/pcint5) pb4 (miso/pcint4) pb3 (mosi/pcint3) pb2 (ss/oc1b/pcint2) pb1 (oc1a/pcint1) pdip 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 32 mlf top view (pcint19/int1) pd3 (pcint20/t0) pd4 (pcint26) pa2 vcc gnd (pcint27) pa3 (pcint6/clki) pb6 (pcint7) pb7 pc1 (adc1/pcint9) pc0 (adc0/pcint8) pa1 (adc7/pcint25) gnd pc7 (pcint15) pa0 (adc6/pcint24) avcc pb5 (sck/pcint5) (pcint21/t1) pd5 (pcint22/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (pcint17) pd0 (pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) note: bottom pad should be soldered to ground. 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 28 mlf top view (pcint19/int1) pd3 (pcint20/t0) pd4 vcc gnd (pcint6/clki) pb6 (pcint7) pb7 (pcint21/t1) pd5 (pcint22/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3//mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (pcint17) pd0 (pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) pc1 (adc1/pcint9) pc0 (adc0/pcint8) gnd pc7 (pci nt15) avcc pb5 (sck/pcint5) note: bottom pad should be soldered to ground.
3 8008bs?avr?06/08 attiny48/88 1.1 pin descriptions 1.1.1 vcc digital supply voltage. 1.1.2 gnd ground. 1.1.3 port a (pa3:0) (in 32-lead tqfp and 32-pad qfn/mlf packages, only) port a is a 4-bit bi-directional i/o port with internal pull-up resistors (selected for each bit) in 32- lead tqfp and 32-pad qfn/mlf package. the pa3..0 output buffers have symmetrical drive characteristics with both high sink and source capab ility. as inputs, port a pins that are exter- nally pulled low will source current if the pull-up resistors are activated. the port a pins are tri- stated when a reset condition becomes ac tive, even if the clock is not running. 1.1.4 port b (pb7:0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. depending on the clock selection fuse settings, pb6 can be used as input to the internal clock operating circuit. the various special features of port b are elaborated in ?alternate functions of port b? on page 64 and ?system clock and clock options? on page 25 . 1.1.5 port c (pc7, pc5:0) port c is a 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the pc7 and pc5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. as inpu ts, port c pins that are externally pulled low will source current if the pull-up resistors are activated. the port c pi ns are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.6 pc6/reset if the rstdisbl fuse is programmed, pc6 is used as an i/o pin. note that the electrical char- acteristics of pc6 differ from those of the other pins of port c. if the rstdisbl fuse is unprogrammed, pc6 is used as a reset input. a low level on this pin for longer than the minimum pulse wid th will generate a reset, even if the clock is not running. the minimum pulse length is given in table 22-3 on page 201 . shorter pulses are not guaranteed to generate a reset. the various special features of port c are elaborated in ?alternate functions of port c? on page 67 . 1.1.7 port d (pd7:0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the pd7..4 output buffers have symmetrical drive char acteristics with both high sink and source capabilities, while the pd3..0 output buffers have stronger sink capabilities. as inputs, port d
4 8008bs?avr?06/08 attiny48/88 pins that are externally pulled low will source current if th e pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. the various special features of port d are elaborated in ?alternate functions of port d? on page 70 . 1.1.8 av cc av cc is the supply voltage pin for the a/d converter and a selection of i/o pins. this pin should be externally connected to v cc even if the adc is not used. if the adc is used, it is recom- mended this pin is connected to v cc through a low-pass filter, as described in ?analog noise canceling techniques? on page 163 . the following pins receive their supply voltage from av cc : pc7, pc5:0 and (in 32-lead pack- ages) pa1:0. all other i/o pins take their supply voltage from v cc .
5 8008bs?avr?06/08 attiny48/88 2. overview the attiny48/88 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the attiny48/88 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. port c ( 8 ) port b ( 8 ) port d ( 8 ) 16 b it t/c 1 8b it t/c 0 a/d conv. intern a l b a ndg a p an a log comp. s pi twi s ram fl as h eeprom w a tchdog o s cill a tor w a tchdog timer o s cill a tor circ u it s / clock gener a tion power su pervi s ion por / bod & re s et vcc gnd progr a m logic de bu gwire 2 databu s pa[0.. 3 ] (in tqfp a nd mlf) pc[0..7] pb[0..7] pd[0..7] 6 re s et clki cpu port a (4)
6 8008bs?avr?06/08 attiny48/88 the attiny48/88 provides the following features : 4/8k bytes of in-system programmable flash, 64/64 bytes eeprom, 256/512 byte s sram, 24 general purpose i/o lines (28 i/os in 32-lead tqfp and 32-pad qfn/mlf packages), 32 general purpose working registers, two flexible timer/counters with compare modes, internal and external interrupts, a byte-oriented 2-wire serial interface, an spi serial port, a 6-channel 10-bit adc (8 channels in 32-lead tqfp and 32- pad qfn/mlf packages), a programmable watchdog ti mer with internal oscillator, and three software selectable power saving modes. idle mode stops the cpu while allowing timer/coun- ters, 2-wire serial interface, spi port, and inte rrupt system to continue functioning. power-down mode saves the register contents but freezes the oscillator, disablin g all other chip functions until the next interrupt or hardware reset. adc no ise reduction mode stops the cpu and all i/o modules except adc, and helps to minimize switching noise during adc conversions. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot pro- gram running on the avr core. the boot program can use any interface to download the application program in the flash memory. by co mbining an 8-bit risc cpu with in-system self- programmable flash on a monolithic chip, the atmel attiny48/88 is a powerful microcontroller that provides a highly flexible and cost effectiv e solution to many embedded control applications. the attiny48/88 avr is supported by a full suite of program and syst em development tools including: c compilers, macro assemblers, program debugger/simulators and evaluation kits. 2.2 comparison between attiny48 and ATTINY88 the attiny48 and ATTINY88 differ only in memory sizes. table 2-1 summarizes the different memory sizes for the two devices. table 2-1. memory size summary device flash eeprom ram attiny48 4k bytes 64 bytes 256 bytes ATTINY88 8k bytes 64 bytes 512 bytes
7 8008bs?avr?06/08 attiny48/88 3. about 3.1 resources a comprehensive set of development tools, app lication notes and datasheets are available for download at http: //www.atmel.com/avr. 3.2 about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructio ns that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 3.3 data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 3.4 disclaimer typical values contained in this datasheet ar e based on simulations and characterization of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized.
8 8008bs?avr?06/08 attiny48/88 4. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? (0xf8) reserved ? ? ? ? ? ? ? ? (0xf7) reserved ? ? ? ? ? ? ? ? (0xf6) reserved ? ? ? ? ? ? ? ? (0xf5) reserved ? ? ? ? ? ? ? ? (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) reserved ? ? ? ? ? ? ? ? (0xf2) reserved ? ? ? ? ? ? ? ? (0xf1) reserved ? ? ? ? ? ? ? ? (0xf0) reserved ? ? ? ? ? ? ? ? (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) reserved ? ? ? ? ? ? ? ? (0xe6) reserved ? ? ? ? ? ? ? ? (0xe5) reserved ? ? ? ? ? ? ? ? (0xe4) reserved ? ? ? ? ? ? ? ? (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) reserved ? ? ? ? ? ? ? ? (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) reserved ? ? ? ? ? ? ? ? (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) reserved ? ? ? ? ? ? ? ? (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) reserved ? ? ? ? ? ? ? ? (0xc5) reserved ? ? ? ? ? ? ? ? (0xc4) reserved ? ? ? ? ? ? ? ? (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) reserved ? ? ? ? ? ? ? ? (0xc1) reserved ? ? ? ? ? ? ? ? (0xc0) reserved ? ? ? ? ? ? ? ?
9 8008bs?avr?06/08 attiny48/88 (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) twhsr ? ? ? ? ? ? ?twhs 152 (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 ?152 (0xbc) twcr twint twea twsta twsto twwc twen ?twie 149 (0xbb) twdr 2-wire serial interface data register 151 (0xba) twar twa6 twa5 twa4 tw a3 twa2 twa1 twa0 twgce 151 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ?twps1twps0 150 (0xb8) twbr 2-wire serial interface bit rate register 149 (0xb7) reserved ? ? ? ? ? ? ? ? (0xb6) reserved ? ? ? ? ? ? ? ? (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) reserved ? ? ? ? ? ? ? ? (0xb3) reserved ? ? ? ? ? ? ? ? (0xb2) reserved ? ? ? ? ? ? ? ? (0xb1) reserved ? ? ? ? ? ? ? ? (0xb0) reserved ? ? ? ? ? ? ? ? (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh timer/counter1 ? output compare register b high byte 108 (0x8a) ocr1bl timer/counter1 ? output compare register b low byte 108 (0x89) ocr1ah timer/counter1 ? output compare register a high byte 108 (0x88) ocr1al timer/counter1 ? output compare register a low byte 108 (0x87) icr1h timer/counter1 ? input capture register high byte 109 (0x86) icr1l timer/counter1 ? input capture register low byte 109 (0x85) tcnt1h timer/counter1 ? counter register high byte 108 (0x84) tcnt1l timer/counter1 ? counter register low byte 108 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ?107 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 106 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 104 (0x7f) didr1 ? ? ? ? ? ? ain1d ain0d 155 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 171 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
10 8008bs?avr?06/08 attiny48/88 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux ? refs0 adlar ? mux3 mux2 mux1 mux0 167 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 170 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 168 (0x79) adch adc data register high byte 169 (0x78) adcl adc data register low byte 169 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) reserved ? ? ? ? ? ? ? ? (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 109 (0x6e) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 82 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 54 (0x6c) pcmsk1 pcint15 pcint14 pcint13 p cint12 pcint11 pcint10 pcint9 pcint8 54 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pc int4 pcint3 pcint2 pcint1 pcint0 54 (0x6a) pcmsk3 ? ? - - pcint27 pcint26 pcint25 pcint24 54 (0x69) eicra ? ? ? ?isc11isc10isc01isc00 50 (0x68) pcicr ? ? ? ? pcie3 pcie2 pcie1 pcie0 52 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register 30 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr prtwi ?prtim0 ? prtim1 prspi ?pradc 35 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 31 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 44 0x3f (0x5f) sreg i t h s v n z c 9 0x3e (0x5e) reserved ? ? ? ? ? ? ? ? 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 12 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr ? ? ? ctpb rflb pgwrt pgers selfprgen 179 0x36 (0x56) reserved ? ? ? ? ? 0x35 (0x55) mcucr ? bpds bpdse pud ? ? ? ? 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 44 0x33 (0x53) smcr ? ? ? ? ?sm1sm0se 36 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) dwdr debugwire data register 173 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 154 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 122 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x 121 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 120 0x2b (0x4b) gpior2 general purpose i/o register 2 24 0x2a (0x4a) gpior1 general purpose i/o register 1 24 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) ocr0b timer/counter0 output compare register b 82 0x27 (0x47) ocr0a timer/counter0 output compare register a 81 0x26 (0x46) tcnt0 timer/counter0 (8-bit) 81 0x25 (0x45) tccr0a ? ? ? ? ctc0 cs02 cs01 cs00 80 0x24 (0x44) reserved ? ? ? ? ? ? ? ? 0x23 (0x43) gtccr tsm ? ? ? ? ? ? psrsync 112 0x22 (0x42) reserved ? ? ? ? ? ? ? ? 0x21 (0x41) eearl eeprom address register low byte 22 0x20 (0x40) eedr eeprom data register 22 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 22 0x1e (0x3e) gpior0 general purpose i/o register 0 24 0x1d (0x3d) eimsk ? ? ? ? ? ?int1int0 51 0x1c (0x3c) eifr ? ? ? ? ? ? intf1 intf0 52 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
11 8008bs?avr?06/08 attiny48/88 note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 ? 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 ? 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the attiny48/88 is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 ? 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) pcifr ? ? ? ? pcif3 pcif2 pcif1 pcif0 53 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) reserved ? ? ? ? ? ? ? ? 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 110 0x15 (0x35) tifr0 ? ? ? ? ? ocf0b ocf0a tov0 82 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) portcr bbmd bbmc bbmb bbma pudd pudc pudb puda 72 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) porta ? ? ? ? porta3 porta2 porta1 porta0 74 0x0d (0x2d) ddra ? ? ? ? dda3 dda2 dda1 dda0 74 0x0c (0x2c) pina ? ? ? ? pina3 pina2 pina1 pina0 74 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 74 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 74 0x09 (0x29) pind pind7 pind6 pi nd5 pind4 pind3 pind2 pind1 pind0 74 0x08 (0x28) portc portc7 portc6 portc 5 portc4 portc3 portc2 portc1 portc0 73 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 73 0x06 (0x26) pinc pinc7 pinc6 pi nc5 pinc4 pinc3 pinc2 pinc1 pinc0 74 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 73 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 73 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 73 0x02 (0x22) reserved ? ? ? ? ? ? ? ? 0x01 (0x21) reserved ? ? ? ? ? ? ? ? 0x00 (0x20) reserved ? ? ? ? ? ? ? ? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
12 8008bs?avr?06/08 attiny48/88 5. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1
13 8008bs?avr?06/08 attiny48/88 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
14 8008bs?avr?06/08 attiny48/88 6. ordering information 6.1 attiny48 note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging alternative, complies to the european direc tive for restriction of hazardous substances (rohs direc- tive).also halide free and fully green. 3. maximum frequency. see figure 22-1 on page 200 . speed (mhz) power supply ordering code package (1) operational range 12 (3) 1.8 ? 5.5 attiny48-au attiny48-mmu attiny48-mu attiny48-pu 32a 28m1 32m1-a 28p3 industrial (-40 c to 85 c) package type 32a 32-lead, thin (1.0 mm) plastic quad flat package (tqfp) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45 mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50 mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
15 8008bs?avr?06/08 attiny48/88 6.2 ATTINY88 note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging alternative, complies to the european direc tive for restriction of hazardous substances (rohs direc- tive).also halide free and fully green. 3. maximum frequency. see figure 22-1 on page 200 . speed (mhz) power supply ordering code package (1) operational range 12 (3) 1.8 ? 5.5 ATTINY88-au ATTINY88-mmu ATTINY88-mu ATTINY88-pu 32a 28m1 32m1-a 28p3 industrial (-40 c to 85 c) package type 32a 32-lead, thin (1.0 mm) plastic quad flat package (tqfp) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45 mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50 mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
16 8008bs?avr?06/08 attiny48/88 7. packaging information 7.1 32a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 32a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ common dimensions (unit of measure = mm) symbol min nom max note
17 8008bs?avr?06/08 attiny48/88 7.2 28m1 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. a 2 8 m1 9/7/06 2 8 m1, 2 8 -p a d, 4 x 4 x 1.0 mm body, le a d pitch 0.45 mm, 2.4 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) s ide view pin 1 id bottom view top view note: the termin a l #1 id i s a l as er-m a rked fe a t u re . d e e k a1 c a d2 e2 y l 1 2 3 b 1 2 3 0.45 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0. 8 0 0.90 1.00 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.20 ref d 3 .95 4.00 4.05 d2 2. 3 5 2.40 2.45 e 3 .95 4.00 4.05 e2 2. 3 5 2.40 2.45 e 0.45 l 0. 3 5 0.40 0.45 y 0.00 ? 0.0 8 k 0.20 ? ? r 0.20
18 8008bs?avr?06/08 attiny48/88 7.3 28p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28p3 , 28-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 28p3 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb b2 (4 places) common dimensions (unit of measure = mm) symbol min nom max note a 4.5724 a1 0.508 d 34.544 ? 34.798 note 1 e 7.620 8.255 e1 7.112 7.493 note 1 b 0.381 0.533 b1 1.143 1.397 b2 0.762 1.143 l 3.175 3.429 c 0.203 0.356 eb 10.160 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
19 8008bs?avr?06/08 attiny48/88 7.4 32m1-a 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 3 2m1-a , 3 2-p a d, 5 x 5 x 1.0 mm body, le a d pitch 0.50 mm, e 3 2m1-a 5/25/06 3 .10 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d1 d e1 e e b a 3 a2 a1 a d2 e2 0.0 8 c l 1 2 3 p p 0 1 2 3 a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a 3 0.20 ref b 0.1 8 0.2 3 0. 3 0 d d1 d2 2.95 3 .10 3 .25 4.90 5.00 5.10 4.70 4.75 4. 8 0 4.70 4.75 4. 8 0 4.90 5.00 5.10 e e1 e2 2.95 3 .10 3 .25 e 0.50 b s c l 0. 3 0 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec s t a nd a rd mo-220, fig. 2 (anvil s ing u l a tion), vhhd-2. top view s ide view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k
20 8008bs?avr?06/08 attiny48/88 8. errata 8.1 errata attiny48 no errata. 8.2 errata ATTINY88 no errata.
21 8008bs?avr?06/08 attiny48/88 9. datasheet revision history please note that page references in this section refer to the current revision of this document. 9.1 rev. 8008b - 06/08 9.2 rev. 8008a - 06/08 1. updated introduction of ?i/o-ports? on page 55 . 2. updated ?dc characteristics (1) ? on page 198 . 3. added ?typical charateristics? on page 212 . 1. initial revision.
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